The present invention is directed to electronic packaging in general, and specifically, a method to form additional surface plating metallization on post-fired MLC substrates.
The present invention has been developed as an alternative to current thin-films repair approaches currently used in the electronic packaging industry. The present invention is also an alternative to the related application referenced above, where a laser beam is used to form a trench on a lapped substrate defining the path of a desired repair conductor from an isolated defective net via to an alternate repair net via. Once the trench is formed, a seed layer is sputtered or evaporated, covering at least a portion of the surface of the substrate and subsequently the bottom and sides of the laser formed trench. The trench is then completely filled by either continued sputtering of the desired metallurgy, or alternately, electroplated. The substrate is then lapped and polished to remove the metallurgy on the surface of the substrate exposing just the repair conductor metallurgy in the now filled trench.
A requirement of the related process is that the substrate must be planarized. This presents several necessary process steps and may introduce other defects which must be addressed. Attempts to create a repair path by using a lift-off mask on non-planar substrates have been unsuccessful. In these methods, a lift-off mask would be placed on the substrate and the laser trench formed through it to expose the substrate surface. The lift-off mask would be left in place when the substrate is seeded and the trench filled with the conductor metallurgy. The lift-off mask, which must now be removed, is completely covered and is fully attached to the repair metallurgy. Removal is now difficult and may introduce undesirable defects to the repair area.
The present invention addresses a means to repair an electrical conductor on a non-planar substrate without the above difficulties. A dual in-situ lift-off mask is disclosed as a means to post-fire personalize Multi-Layer Ceramic (MLC) substrates. The disclosed method can be used as a means to form additional Top Surface Metallization (TSM) wiring used for Engineering Changes (EC""s) or repair of internal wiring defects on planar and non-planar substrates. This process has been developed as an alternative to the thin-film repair approach currently used in the manufacture of MLC substrates.
These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.
The purposes and advantages of the present invention have been achieved by providing a method to form surface plating metallization on a substrate comprising the steps of: providing a substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between the top and bottom surface and between top surface vias; applying a first layer of tape on the top surface; applying a second layer of tape on the first layer of tape; creating a first path through both the first layer of tape and the second layer of tape, to expose a portion of the top surface, the first path contacting at least one conductive via on the top surface; creating a second path through the second layer of tape to expose a portion of the first layer of tape and intersecting with the first path wherein the second path is connected from the first path to an edge of the substrate; depositing a seed layer over the surface of the second layer of tape to create a seeded plating path in the first path and a sacrificial seeded conduction path in the second path intersecting with the seeded plating path; removing the second layer of tape while maintaining a seeded plating path in the first path and a sacrificial seeded conduction path on the surface of the first layer of tape; connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate; immersing the substrate in a plating solution and applying current through the sacrificial seeded conduction path to plate the seeded plating path; and removing the first layer of tape to remove the sacrificial seeded conduction path and uncovering a selectively plated substrate surface.
The method may further comprise the steps of: applying a third layer of tape over the sacrificial seeded conduction path prior to plating such that only the ends of said sacrificial seeded conduction path are exposed to prevent the bulk of the sacrificial seeded conduction path from plating.
In a preferred embodiment the first and second paths are formed by laser ablation. The laser power may also be increased such that the laser ablation also forms a trench in the top surface of the substrate coinciding with the first path.
The present invention also provides a method to repair a defective electrical connection in a substrate comprising the steps of: providing a substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between the top and bottom surface; applying a first layer of tape on the top surface; applying a second layer of tape on the first layer of tape; laser ablating an opening in both the first and second tape layers over a defective via; etching the defective via to create a void to a desired depth; filling the void with an insulating material to electrically isolate the defective via; laser ablating a first path through both the first layer of tape and the second layer of tape to expose a portion of the top surface, the first path connecting the isolated defective via to a repair via on the top surface; laser ablating a second path through the second layer of tape to expose a portion of the first layer of tape and intersecting with the first path wherein the second path is routed from the first path to an edge of the substrate; depositing a seed layer over the surface of the second layer of tape to create a seeded plating path in the first path and a sacrificial seeded conduction path in the second path intersecting with the seeded plating path; removing the second layer of tape while maintaining a seeded plating path in the first path and a sacrificial seeded conduction path on the surface of the first layer of tape; connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate; immersing the substrate in a plating solution and applying current through the sacrificial seeded conduction path to plate the seeded plating path; and removing the first layer of tape to remove the sacrificial seeded conduction path and uncovering a selectively plated repair path on the substrate surface.
The present invention also provides a surface plating metallization structure comprising: substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between said top and bottom surface; a first layer of tape on the top surface; a second layer of tape on the first layer of tape; a first path through both the first layer of tape and the second layer of tape exposing a portion of the top surface, the first path contacting at least one conductive via on the top surface; a second path through the second layer of tape exposing a portion of the first layer of tape and intersecting with the first path wherein the second path is connected from the first path to an edge of the substrate; and a seeded plating path in the first path and a sacrificial seeded conduction path in the second path and on the surface of the first layer of tape.
The surface plating metallization structure may further comprise a third layer of tape over the sacrificial seeded conduction path such that only the ends of the sacrificial seeded conduction path are exposed to prevent the bulk of the sacrificial seeded conduction path from plating.